Category Archives: verilog-a

VALint: the NEEDS Verilog-A Checker

An interesting project on nanoHUB is a Verilog-A checker, VALint.

From their abstract

VALint is the NEEDS created, automatic Verilog-A code checker. Its purpose is to check the quality of the Verilog-A code and provide the author feedback if bad practices, common mistakes, pitfalls, or inefficiencies are found.

It is currently in beta. We hope that this project is successful as Verilog-A is the language for sharing compact models between researchers and circuit simulator software companies. The project is open source and can be downloaded. It can also be launched on nanoHUB on their online simulation platform.