Category Archives: EDA

Coventor SEMulator3D 7.0

EE Journal has an overview of new features Coventor SEMulator3D 7.0. Which incorporates new simulation and meshing capabilities.

They discuss new RC extraction for circuit simulation. In addition, they also discuss new 3D meshing export, as well as a built-in TCAD device simulation feature.

DEVSIM under new open source license

The DEVSIM source code is now released under the Apache License, Version 2.0. It was previously under the LGPL 3.0. The license change is intended to promote adoption of the software and attract new contributors. A brief synopsis of the license is here.

The spirit of the Apache License is also more in line with the license terms packages that DEVSIM relies upon. More information about DEVSIM is available from

VALint: the NEEDS Verilog-A Checker

An interesting project on nanoHUB is a Verilog-A checker, VALint.

From their abstract

VALint is the NEEDS created, automatic Verilog-A code checker. Its purpose is to check the quality of the Verilog-A code and provide the author feedback if bad practices, common mistakes, pitfalls, or inefficiencies are found.

It is currently in beta. We hope that this project is successful as Verilog-A is the language for sharing compact models between researchers and circuit simulator software companies. The project is open source and can be downloaded. It can also be launched on nanoHUB on their online simulation platform.