Category Archives: compact modeling

Coventor SEMulator3D 7.0

EE Journal has an overview of new features Coventor SEMulator3D 7.0. Which incorporates new simulation and meshing capabilities.

https://www.eejournal.com/article/five-major-adds-by-coventor/

They discuss new RC extraction for circuit simulation. In addition, they also discuss new 3D meshing export, as well as a built-in TCAD device simulation feature.

VALint: the NEEDS Verilog-A Checker

An interesting project on nanoHUB is a Verilog-A checker, VALint.

From their abstract

VALint is the NEEDS created, automatic Verilog-A code checker. Its purpose is to check the quality of the Verilog-A code and provide the author feedback if bad practices, common mistakes, pitfalls, or inefficiencies are found.

It is currently in beta. We hope that this project is successful as Verilog-A is the language for sharing compact models between researchers and circuit simulator software companies. The project is open source and can be downloaded. It can also be launched on nanoHUB on their online simulation platform.

MOS-AK GSA December 2013

Presentations from the 6th International MOS-AK/GSA Workshop on Dec.11, 2013 in Washington DC are now available from http://www.mos-ak.org/washington_dc_2013/.

It was organized to discuss SPICE/compact modeling and its standardization. There are presentations about the the various compact modeling initiatives going on in industry and academia.

You can keep track of MOS-AK’s work by signing up for their mailing list at: http://www.mos-ak.org/. They also have a listing of future events concerning compact modeling.