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Verilog A Best Practices Paper

The IEEE Journal of the Electron Devices Society has published an article titled:
Best Practices for Compact Modeling in Verilog-A

The article is freely available for download via open access. It covers how to avoid many of the pitfalls in using Verilog-A compact modeling. It is unclear if this might be related to the effort described in our previous post.

This entry was posted in compact modeling, EDA, SPICE, verilog-a on January 1, 2016 by Juan.

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